Modular computer system



Dec. 31, 1968 J p, ANDERSON ET AL 3,419,849

MODULAR COMPUTER SYSTEM Sheet Filed Nov. 50, 1962 SUPERVISORY INTERSYSTEM DATA LINKS SPECIAL REAL-TIME cwcxs & SELECTED DATA CONVERTERS INPUT/OUTPUT CONTROL MODULES O N W w v ERFTZA R VE TEMI m DH P KP N" M .l- T 1AA. .JHM A RL Y EEEHA 8 LP lNEN MM A H MsLmJw Y B E u G \l FIN a H vA wi v Tm rllll M .fn V r \m f! C V A W l U A Dec. 31, 1968 J. P. ANDERSON ET AL 3,419,849

MODULAR COMPUTER SY STEM Filed Nov. 30, 1962 Sheet 3 of 61 M08 MC? M66 M05 MC4 M03 MC2 MCI INFORMATION (12 PER MEM. MOD) 3A ACCESS OBTAINED 0 PER MEMMOD) IC-B DESCRIPTOR ERANsEERR PER MEM.MOD.)

IC-A DESCRIPTOR TRANSFER 0 PER MEM. M00.)

INVENTORS. JAMES P. ANDERSON SAMUEL A. HOFFMAN BY EELY FIG.3A FIGSB 35 l-mang ATTORNEY Dec. 31, 1968 J. P. ANDERSON ET AL 3,419,849

MODULAR COMPUTER SYSTEM Sheet Filed NOV. 30, 1962 l OF 52 OUTPUT DUPLLCATE INTERCONNECTTONS REQUIRED WITH IC-A IF THE \NPUT OUTPUT BUS ICB IS SUBSTITUTED IN PLACE OF THE COMPUTER BUS P4 INFORMATIONUZ) MEM MOD ADDRESS(4) REQUEST ACCESSU) READ -WRlTE(I) OESCRIPTORO PER l/O BUS) wEEWEE $538 an??? QEOEEIQ 5 OF 32 OUTPUT LOF52 TNPUT CHANNELS CHANNELS CHANNELS I OF 52 lNPUT CHANNELS DESCRLPTOR RETURN TNTERRUPTLI) eg 1 a x i E. Q M" H W H L X W 4) F|| If f 5 T| r f EA a I r 4 :WH f f W w w T r 5 Fl f f f r r C T f f T. r f f f 2 Fl f f r r r A r If r T. T

[E f f f m l r r f H| TEL r r N T 0 I Y s U DD m I SAMUEL A HOFFMAN LUCILE E. MOTT BY STANLEY J PEZELY FIG.3B

JOSEPH SHTFMAN JOHN A WlLKLNS N ATTORNEY Dec. 31, 1968 J- P. ANDERSON ET AL 3,419,849

MODULAR COMPUTER SY STEM Filed Nov. 30, 1962 Sheet 5 or 61 THIN FILM REGISTERS WITH OCTAL ADDRESSES ASSEMBLED FROM I6-BIT REGISTERS ASSEMBLED FROM IZ-BIT REGISTERS ILOITO OIT I5 INDEX REGISTERSIXRI I6 BITS EAGTI IOO TO I03 PROGRAM STORAGE REGIIPSRI) 4B BITS I o 037 5 |M|T RE(;|5TER5(UM) |6 3 EACH] I04 TO IOT PROGRAM STORAGE REGZIPSRZ) 48 BITS 040 TO 042 INTERRUPT STORAGE REGIISR) 48 BITS T0 INTERRUPT RA REGIIP 48 BITS O44TOO4TREPEATPROGRAMREGIRPR) 64BITS III II REAL TIMEGLDCII IRTC) 24BITSI O5OTOO52SUBROUTINESTORAGEREGISSR)ABBITS I REPEATCOUNTREGISTER (RCRI IZBITST 054 BASE PROGRAM REGISTER IBPR) IGBITS IE BASE ADDRESS REGISTER (BAR) l6 DWI Hi CHARACTER COUNT REG (COR) IZBITTI 057 PROGRAM COUNT REGISTER pc 5 5 I24 T0 I2? THIN FILM C REGISTER ITFG) 48 BITS M su u E BASE ADDRESS R 59$ @TOI52 SREPEAT INGREMENT REGIRIR) I2BITS EACH O62 INDEX INCREMENT REGIXIR) IGBITSI I To I43 STACK I44 TO I47 DGSINTERRUPT BASE ADDRESS REG.(IAR) IGDITS '50 mm STACK 48 BITS 064M165 POWER FAILURE DUMP REGIPDRISZBITS I54 T0157 STACK A 43 B115 @INTERRUPT DUMP REG (IDR I6 BTW I I SUBCOMMAND 3DDI MATRIX & CONTROL m COMPARATOR TAXY UPPER LIMITIXIB BITS LOWER LIMITIYI 8 BITS I. REG 4 BITS M REGISTER I2 BITS TAXI 50B 5006 5007 I6 COMPARATOR 4 d MEMORY MEMORY MOD. ADDRESS FIG 4A ADDRESS &

' DATA TMEMM Dec. 31, 1968 .1. P. ANDERSON ET AL 3,419,849

MODULAR GOMPUTER SYSTEM Filed Nov. 30, 1962 Sheet of 61 SUBCOMMANDS A 1 302i 3020 SUBCOMMANDS L MULTtPLY-DWIDE COUNTEMD) I THIN FILM ADDRESS GATING INTERRUPT REGlDlZBITS SYLLABLE ms) I2 ans FUNCTION REG (F) :2 ans MASK REG.(P&Q) zsens I Qz) 50m ams Q E g TEAJEBJEO O AFNTHMETIC UNIT TDB TMAJMB B REGISTER 45 ans 3 V C ADDER 3032 m gmugw AREGISTER aaens' CREGISTVER mans FIGAB Dec. 31, 1968 J. P. ANDERSON ETAL 3,419,849

MODULAR COMPUTER SYSTEM Filed NOV- 30, 1962 Sheet 7 of 61 MAR TRAMsMM VS AND os CONTROLS M0 CLEARING 0F MAR IIOII "Ill 1 M Me MEMORY ADDRESS INPUT AND COUNTER WARTBC MEMORY ADDRESS CEF REGISTERWIAR) I "0" "1" "o" "l" l 6 s e 69 t [02k TCMIR MAR use) MAR (LS8) DECODER 0500mm I024 r MRP/ CURE 4 MWPW READ I027 scMs AND WRITE SWITCHES. DRIVERS []R0|()6 TIMING I CONTROL STROBE m 1 r I M l X SENSING SINGLE |0|| (64x64) AMP SHOTS I I028 49BIT I PLANES l l 1 I03! I032 F|G.5C I

\ BIDP INFORMATION- DRIVERS l r T w J FIGSA FIGSB IOIO ,NVENTORS. JAMES P. ANDERSON SAMUEL A. HOFFMAN By 'fikfs? ff zsu F|G.5C F|G.5D FIGS figfii iiflfmo ATTORNEY Dec. 31, 1968 J. P. ANDERSON ET AL 3,419,849

MODULAR COMPUTER SYSTEM Filed Nov. 30, 1962 Sheet 8 of 61 4MEMORY MODULE ADDRESS(MMA8,4,2,U CROSSPOINTDESCRIPTOR IREAD LEVEURL) SIGNALS FROM OTHER MEMORY ISTANDARD REouEsRsRmomRo) MODULES FOR INHlBlTlNG IDESCRIPTORI/OAREQUESHDARO) I/OA AND l/OB. IDESCRIPTOR 1/0 8 REouEsnnARm 3 FROM DRIVERS FROM DRWERS g INTOTHER INYOTHER v 6 CABINETS CABINEIS REcEzvERs RECEIVERS RECEIVERS RECEIVERS RECEIVERS RECEIVERS RECEIVERS Russ (PI) BUS4 (P2) BUSS (P5) BUS2(l/0B BUSI (I/OA) iNHlBIT susz lNHlBlT BUSI (B d mm 6) MM d) m0 IEI i ER S M ERER'S DBRO 2 (5i) 5 5 Rama 1' l N\ MODUILE A 0REs SELECTOR n BUS5,'BUS4:BUS3}BUS2BUSI ONTROLS lows IOT04 10705 10102 m0: f |0i09 CONFLICLNIgESOLVER L CONTROLS g BUS SELECTION E A J v; i '3 CONTROLS Q XPIXPHPFXP'XP l BUS5BUS4lBUS3fBUS2EBUSI MASTER CONTROLS SCF RRRRRR MTOXP RME COUNTER LMIRA 'LMIRB m r na CONTROL REGISTER LMIRCELMIRD M m CONTROLS LOAD PARtTY,RM|RA 1 RMIRB,RMIRC LINE DRIVERS TIME RMIRD,RESETPARITY CONTROLS COUNTER TCMIR INVENTORS. IOIH JAMES F! ANDERSON BY fifi ifi dnfi T0 SEVEN OTHER T FIG'5A MEMORY CABINTS a? r MTII 2 ATTORfiZY Dec. 31, 1968 J. P. ANDERSON ET AL 3,419,849

MODULAR COMPUTER SYSTEM Filed Nov. 30, 1962 Sheet 9 of 61 U0 GROUP ADDRESS AND INFORMATION BEXCHANCE 1/0 F; GROUP CONTROL COMPUTERI COMPUTERZ COMPUTERS COMPUTER 4 A EXCHANGE E RECEIVERS I RECEIVERS RECEIVERS BUSS (C|);BUS4 (CZTgBUSS (C5) BUS2II/0BORC4I BUSI II/OA IOIITA IOIITB IOIITC IOIIBB IOII8A IOII9B IOII9A I I BUSZ BUSI MIXERS MIXERS IXS MIXER IX5 MIXER FIG.5B

INPUT BUS SIMULATION SWITCHES INVENTORS. JAMES R ANDERSON SAMUEL A HOFFMAN BY LUCILE E. MOTT STANLEY J. PEZELY JOSEPH SHIFMAN JOHN A. WILKINSON ATTORNEY Dec. 31, 1968 J. P. ANDERSON ET AL 3,

MODULAR COMPUTER SYSTEM Filed Nov. 30, 1962 Sheet of 61 04102 R4703 RG58C/U & LOADS AS BELOW DRIVER(DR)/ FIGS / RECEIVER (RX) UP TO EIGHT RX PER L|NE,TWO LINES PER DR 04104 in grams 1968 J- P. ANDERSON ETAL 3,419,849

MODULAR COMPUTER SYSTEM Sheet Filed NOV. 30, 1962 :55 -32 5oz; a tto s 5% saw 81;; :15

.28 GB V630 Dec. 31, 1968 J. P. ANDERSON ET AL 3,419,849

MODULAR COMPUTER SYSTEM Sheet Filed Nov. 30, 1962 NEE Dec. 31, 1968 J. P. ANDERSON ETAL 3,419,849

MODULAR COMPUTER SYSTEM yed Nov. 30, 1962 Sheet L 01'61 ans BITS |2345e?a9|o|||2 1254sera9mnn2 A, A2 A3 "J BASE ADDRESS INCREMENT 0 1 I A T "A INDEXREG. INDEXREG INDEXREG. I ADDRESS ADDRESS ADDRESS L I N N N N F I T "RC" coum 0F REPETITIONS IA CORE MEMORY J I I A I I RELAT'VEOPERANDADDRESS Ri INCREMENT INCREMENT INCREMENT "s" VARIANT SHIFTAMOUNT CORE MEMORY REILAWVE BRANCH ADDRESS "0'' CHARACTER "T" W THIN HLM REGADDRESS T SHTFT FIELD FIELD "V VARIANT AMOUNT LENGTH BEGTN "L; INCREMENT AMOUNT "Vt" VARIANT v" VARIANT INDEX REG. LIMIT REG [IT I ADDRESS ADDRESS "ID" \ARIANT 1 T 1 1 I I I I I I CORE MEMORY q RELATIVE ADDRESS Dec. 31, 1968 Filed Nov. 30, 1962 READ HEAD" J. P. ANDERSON ETAI.

MODULAR COMPUTER SYSTEM Sheet 2 STORE DIRECTION FETCH FIG. I48

FIRST OPERAND IN STACK (A IS STACK) UNINDEXED SECOND OPERAND ADDRESS IN CORE MEMORY INDEXED STORE LOCATION IN CORE MEM0RY-I DIRECTION I IIIOIOI loolIolIfiL IL TL @3531 1939331 BBBEIIENBBY INBQIBINFB BBBETIENBBY INSTRUCTION A, A2 A3 RELATIVE ADDRESS FOR STORE RELATIVE ADDRESS 00%ig0fl T SECOND OPERAND ADDRESS OF STORE LOCATION FIRST SYLLABLE SECOND SYLLABLE THIRD SYLLABLE FOURTH SYLLABLE 0 IIII 1' IM) SYMBOLIC DESCR|PTI0N1A,+A2 A3 FIG. I5

PROGRAM SYLLABLE PROGRAM SYLLABLE PROGRAM SYLIABLE PROGRAM SYLLABLE PROGRAM WORD l2 BITS I2 BITS I2 BITS I2 BITS ALPHANUMERIC CHARICTHI CHITR. CHZTR CH3TR. CizTR. CH5TR CHGTR CHYTR. DITAWOR BBITS GBITS BBIYs BBIIs BBIIs SBITS GBITS GBITS BINARY DATA i BINARY FRACTION WORD I W 47 BITS 5 BINARY FLOATING- QI MANT'SSA (BINARY FRACTION) POINT DATA i "BITS MANTISSA woBB I8" '8 3s BITS FIG.I6 

1. A MODULAR DATA PROCESSING SYSTEM, COMPRISING IN COMBINATION: A PLURALITY OF IDENTICAL COMPUTER MODULES, A PLURALITY OF MEMORY MODULES, A PLURALITY OF INPUT-OUTPUT CONTROL MODULES, A BUS FOR CONNECTING EACH OF SAID INPUT-OUTPUT CONTROL MODULES TO ALL OF SAID MEMORY MODULES, A PLURALITY OF BUSES FOR RESPECTIVELY CONNECTING EACH OF SAID COMPUTER MODULES TO EACH OF SAID MEMORY MODULES, SWITCH INTERLOCK MEANS DISTRIBUTED WITHIN SAID MEMORY MODULES ASSIGNING A PREDETERMINED PRIORITY TO SAID BUSES OVER WHICH ONE OF SAID MEMORY MODULES HAPPENS TO BE SIMULTANEOUSLY ADDRESSED. EACH OF SAID COMPUTER MODULES INCLUDING INTERRUPT MEANS, EACH OF SAID INTERRUPT MEANS RESPONSIVE TO A PLURALITY OF INTERRUPT CONDITIONS CAUSING ITS ASSOCIATED COMPUTER MODULE TO ADDRESS VIA ONE OF SAID PLURALITY OF BUSES A STORAGE LOCATION WITHIN SAID MEMORY MODULES CONTAINING A PROGRAM FOR SERVICING THE PARTICULAR INTERRUPT CONDITION TO WHICH SAID INTERRUPT MEANS IS RESPONDING. EACH OF SAID INTERRUPT MEANS INCLUDING AN INTERRUPT REGISTER PROVIDING EACH COMPUTER MODULE WITH THE CAPABILITY OF RESPONDING TO ALL OF SAID PLURALITY OF INTERRUPT CONDITIONS, MASK REGISTER MEANS CONNECTED TO SAID INTERRUPT REGISTER PERMITTING ITS ASSOCIATED COMPUTER MODULE TO RESPOND ONLY TO SELECTED ONES OF SAID INTERRUPT CONDITIONS, EACH OF SAID MAKE REGISTER MEANS INCLUDING MEANS FOR CHANGING ONE OR MORE OF SAID SELECTED ONES OF SAID INTERRUPT CONDITIONS TO WHICH ITS ASSOCIATED COMPUTER MODULE RESPONDS. 